Traditional approaches for exchanging data over asynchronous interfaces (e.g., DigRF3G interfaces, serializer/deserializer (SerDes) interfaces, and universal serial bus (USB) interfaces) have employed data recovery methods, which generate multiple phases of an internal clock running at a higher rate than the bit rate (e.g., 4× or 8× the bit rate). Each of the multiple clock phases are used to over-sample preamble bits of a data frame. Based on a correlation phase selection algorithm, these interfaces select one of the multiple clock phases to be used in conjunction with sampling data bits in the data frame. These approaches depend on the generation of accurate distributed clock phases, which may be provided by digital dividers or delay lock loops (DLLs).
Unfortunately, in traditional interfaces that employ multiple clock phase generation, the effects of phase imbalance on performance of the interface may be difficult to quantify. Furthermore, such an interface may have relatively high power consumption, because the interface toggles at a rate that is at least twice the data rate, regardless of the data duty cycle. This relatively high power consumption may be compounded in an interface that employs DLLs, because such an interface may continue to generate unwanted phases, even after a phase is selected for the data recovery process. In addition, as these interfaces may employ sampling mechanisms that are highly dependent on phase relationship, data frame sizes typically also are limited.
The designs of data recovery methods for high-speed, asynchronous interfaces have become increasingly complex due to consumer-driven desires for higher supported bit rates. For example, DigRF4G interfaces may be required to support bit rates in excess of 2.5 gigabits/second, and new generations of SerDes interfaces may be required to support bit rates in excess of 1 gigabit/second. For such interfaces, implementing data recovery that depends on multiple clock phases and over-sampling of preamble bits would necessitate the generation of clock signals having rates that are multiples of the already high bit rates. For example, with 4× over-sampling (a typical minimum over-sampling rate), a DigRF4G interface may require the generation of clock signals of about 10 gigahertz (GHz) to implement over-sampling of the preamble bits. Generation of such high-speed clock signals would be a challenge using current technologies, and the increased interface complexity implemented to support the increasingly high bit rates may increase the time to market and/or generally increase the manufacturing costs for devices that include such interfaces.
Accordingly, methods and apparatus are desired for performing asynchronous data recovery, which may exclude the generation or use of multiple clock phases, and which particularly avoid the need to generate clock signals at rates that are multiples of proposed, high-speed bit rates (e.g., multiples of DigRF4G interface bit rates or new generation Ser/Des interface bit rates). Further, high-speed (e.g., 1 gigabit/second bit rates and higher) asynchronous data recovery apparatus are desired, which may include less complicated architectures (e.g., apparatus that exclude DLLs), when compared with traditional asynchronous data recovery apparatus. Further still, high-speed asynchronous data recovery apparatus are desired, which may consume less power in conjunction with performing asynchronous data recovery, when compared with traditional asynchronous data recovery apparatus.